Search - verilog RAM

[Other] verilog_RAM

Description: verilog 实现的一个双口RAM及其控制模块.我通过先存入64个数据在读出仿真通过。-verilog implementation of a dual-port RAM.
Platform: | Size: 1024 | Author: 世海 | Hits:

Description: 压缩包中包含了用Verilog编写的视频控制模块，实现PAL制式到VGA制式的实时转换，同时包含了VGA专用ram配置模块，可直接实用-Compressed package includes the preparation of the video with the Verilog control module, PAL format to achieve real-time conversion to standard VGA, VGA also includes dedicated ram configuration module can be directly useful
Platform: | Size: 79872 | Author: 熊文 | Hits:

[VHDL-FPGA-Verilog] shift_regeister

Description: 用blockram实现移位寄存器，开发语言为verilog hdl-Shift register with blockram achieve the development language for the verilog hdl
Platform: | Size: 148480 | Author: 郭淮 | Hits:

[VHDL-FPGA-Verilog] using_the_block_RAM_in_Spartan-3_FPGA

Description: Spartan-3 系列 FPGA 中的 Block RAM 的使用-using the block RAM in Spartan-3 FPGA
Platform: | Size: 32768 | Author: lishiwei | Hits:

[VHDL-FPGA-Verilog] dual_RAM

Description: actel fusion startkit FPGA开发板试验例程，可实现2k8的双口ram，实现数据存储，缓冲。包含verilog HDL 语言源码-actel fusion startkit FPGA development board test routines, can be realized 2k8' s dual-port ram, achieving data storage, buffer. Language source code contains the verilog HDL
Platform: | Size: 608256 | Author: zhangyujun | Hits:

[VHDL-FPGA-Verilog] blk_write

Description: verilog 块ram写入操作 fpga xilinx ip core-Verilog block_ram module fpga xilinx ip core
Platform: | Size: 2048 | Author: y_gt | Hits:

[Embeded-SCM Develop] LIP2301CORE_Synthesisable-RAM

Description: Verilog Synthesisable RAM source code
Platform: | Size: 214016 | Author: jc | Hits:

[VHDL-FPGA-Verilog] NET2

Description: This file with the wavelet transf Mallat implementation of wavelet Verilog hdl code modules for radi Modelsim 6.6 crack, can be used f A written using Verilog DDR2 cont Simple CPU VHDL implementation an Dual-port RAM design, using Veril Verilog language, a hardware-base FPGA embedded project combat, Man Application FPGA, FPGA-chip hardw Mallat implementation of wavelet Layer of one-dimensional wavelet
Platform: | Size: 1852416 | Author: sansfroid | Hits:

[VHDL-FPGA-Verilog] SOU

Description: 这是用C写的正弦函数定点数据生成代码，内容是生成verilog中RAM或者ROM和Matlab处理时的所用的数据。-It is written with C fixed-point data generate code sine function, the content is generated verilog RAM or ROM, and Matlab in the processing of the data used.
Platform: | Size: 1024 | Author: wolly | Hits:

[VHDL-FPGA-Verilog] ssram

Description: 同步静态RAM读写程序，可用作模块，已通过ISE12.4验证-Synchronous Static RAM read and write procedures, can be used as modules, have been verified by ISE12.4
Platform: | Size: 1024 | Author: koo | Hits:

[VHDL-FPGA-Verilog] AMBA-Bus_Verilog_Model

Description: 该源码包是2.0版本的AMBA总线的Verilog语言模型，主要包括5个部分：AHB总线仲裁器，AHB-APB总线桥接器，AHB总线上从设备ROM模型，AHB总线上从设备RAM模型，参数定义。-This source code package is the model of V2.0 AMBA bus of ARM company, It mainly includes the following five parts: the AHB arbiter,AHB-APB bridge, AHB_Rom_Slave, AHB_Ram_Slave,Defines.
Platform: | Size: 17408 | Author: jinjin | Hits:

[VHDL-FPGA-Verilog] ad-ram

Description: ad采样通过fpga 传输给ram-ad fpga ram verilog
Platform: | Size: 2048 | Author: kaikai | Hits:

[VHDL-FPGA-Verilog] ram

Description: 利用verilog实现的双口RAM。文件包含工程文件，仿真文件，使用方便。-Using verilog implementation of dual-port RAM. File contains the project files, simulation files, easy to use.
Platform: | Size: 219136 | Author: sue | Hits:

[VHDL-FPGA-Verilog] true_dual_port_ram_dual_clock

Description: 双端口ram的verilog程序，经过验证，可编译可用,-dual pot ram
Platform: | Size: 1024 | Author: lee | Hits:

[VHDL-FPGA-Verilog] FIFO-verilog

Description: 本实验完成的是8位异步FIFO的设计，其中写时钟100MHz,读时钟为5MHz，其中RAM的深度为256。当写时钟脉冲上升沿到来时，判断写信号是有效，则写一个八位数据到RAM中；当读时钟脉冲上升沿到来时，判断读信号是有效，则从RAM中把一个八位数据读出来。当RAM中数据写满时产生一个满标志，不能再往RAM再写数据；当RAM中数据读空时产生一个空标志，不能再从RAM读出数据。-In this study, completed the 8-bit asynchronous FIFO design, which write clock 100MHz, read clock is 5MHz, the depth of the RAM 256. When the rising edge of write clock pulse when writing the signal is valid, then write an eight-bit data to RAM when the rising edge of read clock pulse, the judge read the signal is valid, from eight bits of data in RAM to a read out. When RAM is full of data to generate a full mark, can not go down RAM write data when the RAM data read empty an empty sign, can not read data from RAM.
Platform: | Size: 333824 | Author: 肖波 | Hits:

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[Other] verilog_RAM

[VHDL-FPGA-Verilog] VGA

[VHDL-FPGA-Verilog] shift_regeister

[VHDL-FPGA-Verilog] using_the_block_RAM_in_Spartan-3_FPGA

[VHDL-FPGA-Verilog] dual_RAM

[VHDL-FPGA-Verilog] blk_write

[Embeded-SCM Develop] LIP2301CORE_Synthesisable-RAM

[VHDL-FPGA-Verilog] NET2

[VHDL-FPGA-Verilog] SOU

[VHDL-FPGA-Verilog] ssram

[VHDL-FPGA-Verilog] AMBA-Bus_Verilog_Model

[VHDL-FPGA-Verilog] ad-ram

[VHDL-FPGA-Verilog] ram

[VHDL-FPGA-Verilog] true_dual_port_ram_dual_clock

[VHDL-FPGA-Verilog] FIFO-verilog

[VHDL-FPGA-Verilog] ram

[VHDL-FPGA-Verilog] RAM

[VHDL-FPGA-Verilog] verilog-code

[VHDL-FPGA-Verilog] verilog--sram

[VHDL-FPGA-Verilog] Verilog

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